Generally, semiconductor devices may be filled with regions having various densities of both active areas. In particular, semiconductor devices may have both areas of high pattern density next to areas of low pattern density. Such a difference in density between high pattern density areas and low pattern density areas can become a problem during formation of isolation structures such as shallow trench isolations (STIs). Because there are more structures in the high pattern density areas, the deposition of material in the formation of the STIs into these areas leads to a difference in the rate of removal when, e.g., a chemical mechanical polish is performed. With this, a faster polish rate can occur in the low pattern density area and a slower polish rate can occur in the high pattern density area.
With this difference in polish rates also comes a difference in the step height between STIs and the active areas in the high pattern density area and the step height between STIs and active areas in the low pattern density area. This difference in step height of the STIs can affect not only the length (Le) and impedance (Ze) of adjacent transistors, but can also affect the actual shape of a subsequently formed gate. For example, if the STI has a positive step height (wherein a slower polish rate has caused the STI to extend above a substrate), subsequent lithographic masks will be formed slightly off, causing the gate to be wider than desired and forming an “icicle” shape. Additionally, if there is a negative step height (wherein a faster polish rate has caused the STI to be recessed within the substrate), the subsequent effects on the lithographic masks will cause the subsequently formed gates to be thinner than desired and forming a “dogbone” shape.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.